Metal lines are used in semiconductor devices to connect components or individual points together. The metal lines are isolated from each other by dielectrics. A typical interconnect line used in semiconductor devices, for instance as is used in CMOS 18 or CMOS 18 shrink, is shown in FIG. 1. The line 2 consists of a main, conductive metal layer of aluminium-copper alloy (AlCu layer) 4, with a Ti rich TiN layer 6 above and a Ti rich TiN underlayer 8, below.
In an alternative (not shown), both Ti rich TiN layers are replaced with a TiN layer on top of a Ti layer. Such a combination is, for instance shown in published patent document EP-A-0,875,923. According to that document, it is critical that the bottom Ti underlayer has a thickness of from about 90 to about 110 Angstroms (10−10 m). It is exemplified by a metal stack as follows:x ÅTi/100 ÅTiN/2300 ÅAl (0.5% Cu)/50 ÅTi/400 ÅTiNwhere there were five different thicknesses x between 30 and 200 (Å).
A similar combination is shown in published patent document U.S. Pat. No. B2-6,346,480, where the exemplified stack is:30 nm Ti/100 nm TiN/450 nm Al—Cu/15 nm Ti/50 nm TiN.
Similar combinations of varying thicknesses are also shown in a number of other published patent documents, for example: U.S. Pat. No. B1-6,319,727 and U.S. Pat. No. 6,080,657. Other combinations are also known, for instance a TiN or Ti underlayer, beneath a TiAl3 layer, beneath a main Aluminium layer beneath another TiN or Ti layer.
The intervening dielectrics between such known lines are deposited by way of chemical vapour deposition (CVD) techniques. However, the encapsulating dielectrics subject the metal lines to mechanical tensile stresses, which result in stress induced voids (SIV) in the metal lines. Intrinsically, such dielectrics are compressive films, i.e. the AlCu lines which are encapsulated experience tensile stresses. The stress voids occur as a result of the tensile forces on the grain boundaries. This problem is pronounced when the intermetal dielectric is deposited using high density plasma (HDP) methods, as such materials are known to impart large tensile stresses on the metal lines.
The tensile stresses are also increased when the coefficient of thermal expansion (CTE) between the AlCu interconnect metal lines differ. Thus, when the semiconductor device experiences thermal cycles during its lifetime, the tensile stresses induced on the metal lines are large enough to cause SIVs.
Typically SIVs are wedge shaped voids in the metal lines. Such voids/cracks occur where the yield stress is lowest, which is at the grain boundaries of the metal interconnect lines. In general, the methodology for evaluating such voids is by subjecting the completed semiconductor devices to a period of thermal stress and then checking for SIVs by delayering away the passivating dielectrics and inspecting under a scanning electron microscope (SEM). Typical stress voids are wedge shaped and occur at the grain boundaries where the yield stress is lowest. FIGS. 2A and 2B show two views of three AlCu metal interconnect lines 2 after the passivating dielectrics are removed. FIG. 2A is a top plan view and FIG. 2B an isometric view. A stress induced void 10 is clearly present on one of the lines, being approximately 300 nm long and 100 nm across the width of the line (about one third of the width of the line). However, the voids can be any size and depth, even to the extent of breaking the metal line.
SIVs in AlCu interconnect lines are a reliability concern, as the increase in the resistance of the metal line (as a result of the reduced cross sectional area) will result in device failure, either as a consequence of the increase in the RC time delay constant or because of structural failure if the metal opens. If a fabrication plant is unable to control or avoid such voids, it is unable to obtain suitable qualification for production of relevant devices.